The control for an industrial motor or a server power source for example is performed by driving half-bridge connection semiconductor devices. As an IC for driving these semiconductor devices, there is an HVIC (High Voltage IC). The use of the HVIC allows both of an upper level-side semiconductor device and a lower level-side semiconductor device of a half-bridge circuit driven by a high potential power source to be driven by one IC. The HVIC receives a control signal of a microcomputer for example to output a signal for driving the semiconductor device. The HVIC includes therein a level-shift circuit in order to drive the upper level-side semiconductor device in particular by a low potential signal.
The HVIC includes therein a level up shift circuit for transmitting a signal from the low side to the high side and a level down shift circuit for transmitting a signal from the high side to the low side. Generally, a level up shift circuit uses an N channel-type semiconductor switching element and a level down shift circuit uses a P channel-type semiconductor switching element. When a half-bridge circuit is switched, a reference potential of a high side region changes from a low potential to a high potential or from a high potential to a low potential.
FIG. 1 illustrates a circuit configuration using a conventional level-shift circuit disclosed in Patent Literature 1. FIG. 1 illustrates a circuit including an output circuit 10 including a high potential-side switching element 11 and a low potential-side switching element 12, a high potential-side driving circuit 20, and a low potential-side driving circuit 30. The high potential-side driving circuit 20 is connected to a gate terminal of the high potential-side switching element 11 of the output circuit 10. The low potential-side driving circuit 30 is connected to the gate terminal of the low potential-side switching element 12 of the output circuit 10.
The output circuit 10 is composed of the high potential-side switching element 11 and the low potential-side switching element 12 that are serially connected. A high voltage power source 13 supplies electric power to a load 14 via the high potential-side switching element 11. The load 14 is a load that receives the supply of a voltage (electric power) from the half-bridge circuit. The load 14 is connected between the connecting point Vs of the high potential-side switching element 11 and the low potential-side switching element 12 (the potential of the connecting point Vs is also represented by the connecting point Vs) and a grounding potential.
The high potential-side switching element 11 and the low potential-side switching element 12 are turned ON/OFF in a complementary manner so that one is ON and the other is OFF except for a dead time during which the former and the latter are both OFF. When the low potential-side switching element 12 is ON, the potential of the connecting point Vs is a grounding potential and, when the high potential-side switching element 11 is ON, the potential of the connecting point Vs is the output voltage of the power source 13.
The high potential-side driving circuit 20 includes a latch malfunction protection circuit 21, a latch circuit 22, a high side driver 23, a power source 24, resistances R1 and R2, level-shift transistors 25 and 26, and diodes D1 and D2. The latch malfunction protection circuit 21, the latch circuit 22, the high side driver 23, and the low potential-side power source terminal of the power source 24 are connected to the connecting point Vs.
The input of the gate of the level-shift transistor 25 is a set signal that is an input signal to the level-shift circuit of the high potential-side driving circuit 20. The input of the gate of a level-shift transistor 26 is a reset signal that is an input signal to the level-shift circuit of the high potential-side driving circuit 20. The set signal is a signal that instructs the timing at which the ON period of the high potential-side switching element 11 is started (or the OFF period is ended). The reset signal is a signal that instructs the timing at which the OFF period of the low potential-side switching element 12 is started (or the ON period is ended). The set signal and the reset signal are pulse input signals that are not turned ON simultaneously. The level-shift transistors 25 and 26 can use an N channel-type semiconductor switching element.
The input of latch malfunction protection circuit 21 is level-shift output signals setdrn (hereinafter referred to as a setdrn signal) and resdrn (hereinafter referred to as a resdrn signal). When there is a change in the potential of the connecting point Vs, an error signal is caused that is called a dv/dt noise due to the parasitic capacitances Cds1 and Cds2 for example between the source and drain of the level-shift transistors 25 and 26. Then, the setdrn signal and the resdrn signal both have an H level or an L level, undesirably causing the set instruction and the reset instruction to the latch circuit 22 to be valid. In this case, the latch malfunction protection circuit 21 is a circuit to prevent the setdrn signal and the resdrn signal from being directly transmitted to the latch circuit 22 by causing the output to have a high impedance for example. The latch malfunction protection circuit 21 is a circuit that functions, when there is no dv/dt noise, to allow the setdrn signal and the resdrn signal to be directly passed and output and, when there is a dv/dt noise, to output a signal processed based on the setdrn signal and the resdrn signal (by setting one output signal to allow the signal to have an H level when the setdrn signal and the resdrn signal are the ones to set the latch circuit 22 or to allow the output to have a high impedance when the setdrn signal and the resdrn signal are the ones to reset the latch circuit 22 for example) or to block the passage of the setdrn signal and the resdrn signal.
The input of the latch circuit 22 is an input signal from the latch malfunction protection circuit 21 and stores therein a value set or reset depending on whether the input signal is L or H to output the value. When the input has a high impedance, the latch circuit 22 retains and outputs a value stored immediately before when the input had the high impedance.
The output terminal of the high side driver 23 is connected to the gate terminal of the high potential-side switching element 11. The output terminal of the high side driver 23 outputs a signal HO depending on the output of the latch circuit 22 to control the ON/OFF of the high potential-side switching element 11.
The diodes D1 and D2 have anodes connected to the connecting point Vs. The cathode of the diode D1 is connected to the connecting point Vsetb. The cathode of the diode D2 is connected to the connecting point Vrstb. The diodes D1 and D2 function to clamp the voltages Vsetb and Vrstb so that the voltages Vsetb and Vrstb are prevented from being equal to or lower than the potential Vs and to protect the latch malfunction protection circuit 21 so that the latch malfunction protection circuit 21 does not receive an overvoltage.
The low potential-side driving circuit 30 includes a low side driver 31 that controls the ON/OFF of the low potential-side switching element 12 and a power source 32 that supplies a power source to the low side driver 31. The low side driver 31 amplifies the signal S that instructs the ON/OFF of the low potential-side switching element 12 to output the signal S to the gate terminal of the low potential-side switching element 12. As a result, the low potential-side driving circuit 30 turns ON the low potential-side switching element 12 when the signal S inputted to the low side driver 31 has a H (High) level and turns OFF the low potential-side switching element 12 when the signal S has an L (Low) level.
FIG. 2 illustrates a conventional level-shift circuit disclosed in Patent Literature 2. The level-shift circuit shown in FIG. 2 is different from the level-shift circuit shown in FIG. 1 mainly in a malfunction prevention circuit and a latch circuit provided at the high side.